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A new controller architecture for image stable displays is described which enables lower system hardware cost and complexity, easier access to ultra‐low and zero power states, and expanded flexibility in panel resolution, signal timing, and operating mode. This architecture is contrasted with currently available EPD controllers, and a specific implementation of the approach with 8 bits of storage per screen pixel is examined in use with two example EPD panels.

An enhanced functionality controller IC for active matrix electrophoretic displays has been developed. The IC offers the ability to run up to 16 updates concurrently on different areas of the screen, allowing multiple image modification operations to proceed independently in time and space. This capability, when combined with the latest commercial EPD materials and waveforms, enables compelling improvements to interactive usage modes like pen input and fast UI operation. Supported panel resolution range and system integration features have also been significantly expanded.

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EM-Cube is a VLSI architecture for low-cost, high quality volume rendering at full video frame rates. Derived from the Cube-4 architecture developed at SUNY at Stony Brook, EM-Cube computes sample points and gradients on-the-fly to project 3-dimensional volume data onto 2-dimensional images with realistic lighting and shading. A modest rendering system based on EM-Cube consists of a PCI card with four rendering chips (ASICs), four 64Mbit SDRAMs to hold the volume data, and four SRAMs to capture the rendered image. The performance target for this configuration is to render images from a 256 3 16 bit data set at 30 frames/sec.The EM-Cube architecture can be scaled to larger volume data-sets and/or higher frame rates by adding additional ASICs, SDRAMs, and SRAMs. This paper addresses three major challenges encountered developing EM-Cube into a practical product: exploiting the bandwidth inherent in the SDRAMs containing the volume data, keeping the pin-count between adjacent ASICs at a tractable level, and reducing the on-chip storage required to hold the intermediate results of rendering.