37.2: Improved Electronic Controller for Image Stable Displays

Abstract

A new controller architecture for image stable displays is described which enables lower system hardware cost and complexity, easier access to ultra‐low and zero power states, and expanded flexibility in panel resolution, signal timing, and operating mode. This architecture is contrasted with currently available EPD controllers, and a specific implementation of the approach with 8 bits of storage per screen pixel is examined in use with two example EPD panels.

62.1: Invited Paper: System Integration of Electronic Paper Displays

“…More recently, a new EPD controller architecture has been developed by E Ink. This new design uses the existing LCD interface found in most mobile device processors to transfer image data to the EPD controller [4]. The host system frame buffer, which would normally hold a bitmapped version of the image to be displayed, is re-formatted to hold both current and previous image, as well as driving data used by the EPD controller.…”

46.3: High Performance Active Matrix Electrophoretic Display Controller

“…A complementary second generation chip, called Metronome, was introduced in 2006 which offered reduced hardware cost and complexity by utilizing the output of a TFT LCD controller on the host processor [5]. By shifting timing generation and frame storage to the host system and performing the image to impulse translation described by the waveform on every pixel on the fly, this IC cut the controller chip count from 4 to 1 and could transparently support a wider variety of waveforms (including 3 bit grayscale) and panel sizes.…”