ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity in mass production of immersion lithography. In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer. We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse [1,2], which was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.

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In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process manufacturability performance of the CLEAN TRACK TM LITHIUS Pro™-i/ TWINSCAN™ XT:1900Gi lithocluster at the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUS™ i+/TWINSCAN XT:1700i. 1 In this work, process performance with regards to critical dimension uniformity and defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.