Ferroelectric random access memory (FRAM) has been commercialized for about 20 years and its reliability has been well proven all over the world. In the recent Internet of Things (IoT) era, it also plays important roles to particularly in edge computing because of its high writing speed, high rewriting endurance, and low writing energy consumption. We review the history of semiconductor memories using ferroelectrics and overview the progresses of the new ferroelectrics and promising ferroelectric applications in the future.

A 0.18 pn 4 Mbit FRAM for high performance System on Chip (Soc) was developed Large polarization and higb reliability were achieved with a (111) oriented MOCVD PZT We also developed new OpaCitor fabrication technology, receswd Ir bamier and high t e m p e m one mask etching. We achieved embedded FRAM with only two additional masks for conventional CMOS process.

HgCdTe n+p DIODES 1255performance. The diodes exhibit high zero bias resistance and excellent uniformity and the dense SiN~ film stabilizes the diodes in humid conditions. ABSTRACTWe grew a single crystalline beta silicon carbide (B-SiC) layer at 1000~ on a Si off-axial (111) substrate without using a buffer layer from a gas system of SiHC13-C3Hs-H2. The heterojunction between epitaxially doped n-type B-SiC and p-type Si showed a diode ideality factor of 1.0-1.1, indicating that B-SiC has a high potential for use as a wide gap emitter material.Beta silicon carbide (B-SiC) shows promising properties for use in high speed and high power devices working at high temperature. This comes from the physical properties of B-SiC, i.e., a thermal conductivity of 5 W/cm~ a satu-) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 132.174.255.116 Downloaded on 2015-03-16 to IP

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in I on current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.