A novel CMOS architecture utilizing tensilekompressive silicon nitride capping layers to induce tensilekompressive strain in NMOSFETPMOSFET channel regions was developed. NMOSFET device delivers 1.05mA/pm on-current for 7OnA/pm off-current at 1V drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N-and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub40nm gate length.

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NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and IV supply voltage fabricated NMOSFET delivers 1.00mA/pm drive current for off-state current of 4 M p m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability [I-3). Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

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