No abstract

No abstract

Abstract. The paper reports the development of a case study for creating a unified development environment for the process of code generation from Matlab/Simulink into both HDL and C languages of FPGA and DSP targets. The FPGA is used for the Hardware-In-the-Loop (HIL) simulation of the high power, main circuit of a simple solar-based battery charger while the control functions belonging to this system are implemented in a DSP. The case study is planned to be a building block of the HIL simulation of either such a sophisticated, cyber-physical system like a microgrid which connects various forms of energy produced by renewable sources.

The advances in FPGA technology have enabled fast real-time simulation of power converters, filters and loads. HIL (Hardware-in-the-Loop) simulators taking advantage of this technology have revolutionized control hardware and software development for power electronics. Switching frequencies in today's power converters are getting higher and higher, so reducing calculation time steps in HIL simulators is critical, especially if simulating lower power circuits. Faster calculation can be achieved with simpler models or lower resolution. Both possibilities require the validation of the FPGA-synthesizable simulation models to check whether they are correct representations of the simulated main circuit or not. The subject of this paper is a validation method, which treats the simulation error similar as production variance, which can be measured between different instances of the original main circuit.

No abstract