We present a comprehensive study of the impact of NBTI on SRAM V ccmin stability. We describe a novel simulation technique to predict the between -die statistical distribution of V ccmin drift due to NBTI. While the drift is a fundamental phenomenon, we show that by cell design and transistor process optimization, the drift can be reduced to tolerable levels.

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Introductionsignificant, Cause of device performance variation [1]- [7]. Stress induced from shallow trench isolation is found to' influence seriously the mobility and thus the l&OD model for Stress Effect Mechanical stress effect has become a Stress effect could be explained by the mobility change for different layouts. The relationship is :Of the bulk ,where ku is a L-dependent coefficient and SNSB devices [11-[41. The impact Of effect On are defined in the inserted layout of Fig.1, Fig.4 devices are also crucial' [51-[71. %is effect is so shows the model fitting The data basically important and thus should be modeled in SPICE simulation. So far only models for bulk devices are follows the laOD trend but the curve will shift upward with longer channel length, which means proposed [11[31. But devices need fiuther study because their mechancial is different fromIn this paper, we will analyze ku is higher in L=O,5um than in L+.lum, Fig.5 could explain this behavior. As shown in the schematic stress distribution of Fig.5, stress starts the stress effect of SO1 devices and then derive a model for it. at the OD edge and decays toward the center channel region. Only the stress under the channel region has direct impact on the device performance. And according to Fig.5 , even with the same LOD, Fig. 1 shows the drain current shift in the longer devices will suffer higher effective stress percentage at different LOD in comparison with and thus the curve in Fig.4 will move up LOD=lOum, where LOD is the length of OD active accordingly. Basically ku in Eq.1 will follow the region as defined in the inserted layout. As shown lLgate formula. The equation looks like: in this figure, both Bulk and SO1 exhibit the same (2)trend. When the LOD is shnmk, the drain current of bulk and SO1 devices would be degraded significantly. Fig. 2 illustrates the cross-section of Fig. 6 evaluates the width-dependence of stress SO1 devices. As described in [l], the stress in bulk effect and we found it is less sensitive to the devices starts at the edge of OD active region and channel width as compared with the channel length. distributes through the whole device. Note that the Fig.7 shows the drain current shift with different stress in Bulk mainly come from the OD/STI bias conditions. As shown in Fig.7, shift of comer [1] [2]. On the other hand, the STI depth of saturation current is smaller than linear current. It SO1 is much shallower. However, there exists is consistent with some papers that saturation oxide encroachment at the edge of active region, velocity will also change but more slightly than which will bend the silicon film slightly and mobility [4]. Another equation is necessary for this introduce an extra stress source in the devices [5]. phenomenon: Fig.1. Fig.3 further inspects the 17ig.g shows the layouts data. ne Vth variation with respect to different LOD sizes. It shows that stress effect has small impact on Vth in this wafer. However. obvious Vth shift might Comparision between SO1 and Bulk structures, their stress effects...