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A novel dispenser-nozzle-scan coating (NS-coating) method was developed. NS-coating is very useful for reducing the coated volume and its cost. This method has two stages. The first stage is to form a fluid film on the substrate. The second stage is the vacuum drying process to evaporate the solvent with agitation to improve the thickness uniformity. In the first stage, one of the most important parameters of NS-coating is the relationship of the contact angle of the fluid film on the substrate surface to the scan pitch of the dispenser nozzle. The start and end positions of dispensation are also important in terms of avoiding projection. With selecting the solvent of a resist solution on the anti-reflection-layer (ARL) surface and optimizing the start and end positions of dispensation, the thickness uniformity of less than 2% was obtained in the solid state.

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We have investigated micro-void formation mechanism in vias at 45nm-node using OBIRCH method and SEM analysis, and found that micro-void formation is induced by via contour distortion. We have also clarified the correlation between edge roughness of a via pattern and micro-void formation.From this, we conclude that via edge roughness suppression is the key technology for robust interconnects fabrication in 45nm-node and beyond.. Introduction It is well known that the micro-voids in vias degrade yield and reliability. Hence, suppression of micro-voids is indispensable for robust interconnects as the technology generation scales down.To achieve excellent yield and reliability, we have improved several items, such as ILD structure, RIE condition, metallization process and reported as BEOL integration technologies for the 45nm-node [1] [2]. However, it is necessary to secure sufficient process margin in order to sustain high via yield and reliability in mass production.In general, it is not possible to identify the degradation of a single via within a via-chain pattern from electrical evaluation alone. In this paper, we report on efficient micro-voids detection using optical beam induced resistance changes (OBIRCH) method [3], and discuss the mechanism of micro-void formation. ExperimentsTwo layers of dual damascene structures were used for electrical evaluation (shown in Fig.1). The dielectrics consist of hybrid structure: porous organic low-k for IMD, SiOC type low-k for ILD. The target via diameter is 70nm.Miscellaneous types of via-chain test patterns were measured electrically. After that, we tried to locate micro-voids in vias using OBIRCH method, and observed the via contour with SEM.OBIRCH method detects the current change (I) caused by resistance variation (R), which is induced by laser irradiation. In OBIRCH method, we measured the I of via -chain pattern while supplying constant voltage. We detected large I at the high resistance via, and OBIRCH system showed clear bright spot with large contrast at the via, which is called "a bright point".In order to clarify the mechanism of micro-void formation, we analyzed many vias from different test patterns and wafers using three techniques below: 1. Cross-sectional TEM observation 2. The top-view SEM observation of vias at the bright point detected by OBIRCH method. Vias in uniformly dark area is also observed for comparison. The top-view SEM observation of vias in-line Cross-sectional TEM observationWe observed some vias by TEM at bright points and non-bright points detected OBIRCH method. In order to identify the failure mode, we observed many bright points picked up randomly. The top-view SEM observationWe observed top-view of via contour using SEM by the following procedure.(1) We located failure vias by OBIRCH method.(2) The surface of the upper layer wiring (M2) was revealed by mechanical polishing. In order not to damage the via contour, we stopped polishing on the wiring surface, and selectively dissolved Cu using HPM and left barrier-metal intact.(3) ...

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