Patterning strategy and performance of 1.3NA tool for 32nm node lithography

Motomizu, Shoji; Satake, Masaki; Kitamura, Y.; Takahata, Kazuo; Kodera, Katsuyoshi; Fujise, Hiroharu; Ema, Tatsuhiko; Sho, Koutaro; Ishigo, Kazutaka; Kono, Takuya; Asano, Masafumi; Yoshida, Kenji; Kanai, Hideki; Kyoh, Suigen; Harakawa, H.; Nomachi, Akiko; Ishida, Takeshi; Miyashita, K.; Inoue, Soichi

doi:10.1117/12.772201

Cited by 8 publications

(6 citation statements)

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“…Both of these layers should be suitable for single-pass patterning using Cquad or Quasar illumination. [6] Line-end shortening for the Metal-1 layer can be accommodated in the end-gap spacing rule, applied globally to the design.…”

Section: Simulation Results For 32nm Logicmentioning

confidence: 99%

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32nm and below logic patterning using optimized illumination and double patterning

Smayling

Axelrad

2009

SPIE Proceedings

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Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm pitch. It is likely that the node will begin at the upper end of the range, and then shrink by ~10% to a "28nm" node. For the lower end of the range, even with immersion scanners, the Rayleigh k 1 factor is below 0.32. The 22nm logic node should begin with minimum pitches of approximately 70nm, requiring some form of double patterning to maintain k 1 above 0.25.Logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete "freedom" compared to the very regular patterns used in memory. The logic layouts with bends and multiple pitches resulted in larger rules, un-optimized illumination, and a poorly understood process windows with little control of context-dependent "hot spots."[1]The introduction of logic design styles which use strictly one-directional lines for the critical levels now gives the opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give areacompetitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability.[2] These benefits can be extended to ≤32nm logic using selective double pass patterning.

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Section: Simulation Results For 32nm Logicmentioning

confidence: 99%

“…[6] This is often problematic since models for new equipment and processes are usually not available until well into the development project. Fortunately for the foreseeable future, with λ/NA limited to 143nm, the available models are reasonably mature.…”

Section: Modeling and Simulationmentioning

confidence: 99%

32nm and below logic patterning using optimized illumination and double patterning

Smayling

Axelrad

2009

SPIE Proceedings

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“…35) water-based immersion exposure tool, in combination with considerable, yet manageable design rule restrictions and significant resolution enhancement technologies (RET) [3,4] . Without fundamental changes, however, lithography solutions do not exist for 22 nm node along this path.…”

Section: Lithography Technology For 2nm Technologymentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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“…This focus variation is sure to ruin the focus budget in low k1 lithography. From the focus budget of CMOS device (1) , substrate topography is required to be less than 30nm for hp 45-nm generation devices and less than 15nm for hp 32-nm generation devices. Today, for most topographic layers, the chemical mechanical polishing (CMP) technique is applied to achieve global planarization.…”

Section: Introductionmentioning

confidence: 99%

Feasibility studies of coating method for planarization process

Matsunaga

Oori

Katō

et al. 2009

Advances in Resist Materials and Processing Technology XXVI

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The lithography process on topographic substrate is one of the most critical issues for device manufacturing. Topographic substrate-induced focus variation occurs between top position and bottom position in a layer. That is, common depth of focus is reduced. This focus variation is sure to ruin the focus budget in low k1 lithography. From the focus budget of CMOS device (1) , substrate topography is required to be less than 30nm for hp 45-nm generation devices and less than 15nm for hp 32-nm generation devices. In this paper, the authors evaluate a novel concept for hp45-nm generation dual damascene layer for global surface planarization. The novel concept is thin planarization layer with bottom anti-reflecting (BAR) function. This planarization layer with optical performance is materialized by UV crosslink materials and process. This concept is expected to lead to a simpler planarization process. Thin planarization layer with BAR function clear BARC layer and simplifies the etching process. Our study showed that the planarization performance of UV crosslink layer with 100nm thickness was 20nm thickness bias between the field area and dense via hole area. This thickness bias achieved the requirement of hp 45nm generation. Furthermore, fine resist pattern was resolved on the planarization layer by the optimization of acid components and additive.

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Patterning strategy and performance of 1.3NA tool for 32nm node lithography

Cited by 8 publications

References 0 publications

32nm and below logic patterning using optimized illumination and double patterning

32nm and below logic patterning using optimized illumination and double patterning

Challenges of 22 nm and beyond CMOS technology

Feasibility studies of coating method for planarization process

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