We report the design, growth, processing, and characterization of resonant cavity enhanced photodiodes for the midwave infrared at ∼3.72 μm on GaSb. Using AlAsSb/GaSb mirrors, AlAsSb barrier and spacer layers and a thin 96 nm InAsSb absorber, we observed dark current and detectivity behavior superior to common InAsSb nBn detectors in the literature, with peak specific detectivity values of 8×1010 and 1×1010 cm Hz1/2 W−1 measured at 250 K and 300 K, respectively. In the same temperature range, the linewidth of the detector response was <44 nm and the quality factor ∼80. The peak quantum efficiency was >60% where the enhancement due to the resonant cavity was ∼20x. We estimate that the devices can operate close to, or slightly above, the background-limited infrared performance limit imposed on broadband detectors for a 300 K scene.

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

The development of new high-performance Focal Plane Arrays (FPAs) for imaging systems is driven by advances in photodetector material growth and processing, readout integrated circuits and IR detector chip hybridisation/packaging. The hybridisation of the IR detector chip and the readout integrated circuit (ROIC) through flip-chip bonding is a key packaging challenge for pixel arrays with very small indium bumps and 10-30 m pitch sizes. This paper details the development and use of finite element models that can be used to assess and optimise the compression bonding process, and can enable insights into the impact of chip misalignment on the resulting flip-chip quality and the bonding equipment placement accuracy requirements for a given FPA specification. In addition, the fatigue performance of the indium interconnects of different fine pitch FPAs is evaluated and compared. The modelling results point that high quality interconnects and robust, defects-free assembly require micrometre placement accuracy. It is also possible that indium joints of higher resolution, larger size FPAs accumulate less damage under cryogenic temperature cycling compared to less dense, smaller in size, focal plane arrays.