(Invited) Towards a Vertical and Damage Free Post-Etch InGaAs Fin Profile: Dry Etch Processing, Sidewall Damage Assessment and Mitigation Options

Abstract

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

Sub-10 nm plasma nanopatterning of InGaAs with nearly vertical and smooth sidewalls for advanced n-fin field effect transistors on silicon

“…The sidewalls roughness as well as the fins width could be further reduced through a digital etch cycle based on a self-limited oxygen plasma oxidation followed by a diluted H 2 SO 4 rinse for oxide removal, as reported in different studies. 8,14,28…”

“…Great efforts have been invested for enhanced profile verticality, 8 sidewalls smoothness, 9 surface stoichiometry 10 and etch-induced damage mitigation. 8 Indeed, vertical-sidewall FinFETs have demonstrated better performance at low and moderately doped fins while extremely doped FinFETs are more performant when the fins sidewalls are tapered. 11,12 Furthermore, the sidewall roughness, 13 the modification of the surface stoichiometry during the etching, 12 and the ion bombardment-induced damage 14 greatly degrade the MOS interface, causing an important decline in the device reliability and electrical performance.…”

“…Plasma etching of indium-containing III-V semiconductors has been investigated using chlorinated chemistries such as BCl 3 /Cl 2 , 8,15 Cl 2 /N 2 , 16 Cl 2 /H 2 /Ar, 17 Cl 2 /Ar, 18 SiCl 4 , 19 and BCl 3 /SiCl 4 /Ar. 14 Other gas mixtures such as CH 4 /H 2 (Ref.…”

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

“…In these studies, the solutions of TMAH, mixture solution HF:H 2 O 2 :CH 3 COOH and other alkaline solutions have often been used to obtain a SiGe channel [ 22 , 23 , 24 , 25 ]. However, in the traditional FinFET structure, an important problem is the dry-etching damage to the sidewall caused by plasma sputtering in the fin formation process [ 26 , 27 , 28 , 29 ]. Therefore, the wet-etch method is advantageous for the formation of advanced GAA stacked nanowires.…”

Low damage patterning of In0.53Ga0.47As film for its integration as n-channel in a fin metal oxide semiconductor field effect transistor architecture

“…4,5 One of the challenges of InGaAs integration as a channel in a FinFET architecture is the fabrication of the III-V fin. 6,7 It requires the development of the plasma etching process allowing nanometer scale fin definition, with vertical sidewalls and undamaged surfaces (top and sidewalls). Indeed, vertical-sidewall FinFETs have demonstrated better performance at low and moderately doped fins while extremely doped FinFETs are more performant when the fin sidewalls are tapered.…”