Sub-10 nm plasma nanopatterning of InGaAs with nearly vertical and smooth sidewalls for advanced n-fin field effect transistors on silicon

Abstract

This work focuses on the nanopatterning of sub-10 nm InGaAs fins by inductively coupled plasma reactive ion etching for advanced IIIÀV n-fin field effect transistors (n-FinFETs) on silicon. First, different chlorine chemistries have been investigated and compared in order to select the most adequate one for the FinFETs process. Following this analysis, the BCl 3 /SiCl 4 /Ar mixture was selected for the remaining of the work. Thus, a systematic study of the etching process based on this chemistry has been carried out, and the effects of the experimental conditions on the etching kinetics and the sidewalls quality have been revealed. The optimized results depict 8 nm width fins with smooth (line edge roughness %2 nm) and almost vertical (85 6 1) sidewalls, opening the way for sub-10 nm width InGaAs FinFETs on silicon. V

InAs/GaSb thin layers directly grown on nominal (0 0 1)-Si substrate by MOVPE for the fabrication of InAs FINFET

“…Hereafter the PS blocks with a remaining height of 20 nm act as an etch mask for a BCl3/SiCl4/Ar 15/5/20 plasma that etches the InAs layer. This plasma, first studied on InGaAs [20], gives access to an InAs etching rate of 1.6nm/sec. InClx etching byproducts are not volatile at ambient temperature, thus high temperatures are used to promote their desorption.…”

Line edge roughness measurement on vertical sidewall for reference metrology using a metrological tilting atomic force microscope

“…As such, several studies have investigated sidewall roughness measurements using the tilting-AFM technique [16][17][18][19][20] by mostly evaluating sidewall surface roughness expressed in standard deviation of the distance between each point and least-squared plane of point cloud at the sidewall, while the height information is ignored. The LER distribution along the height (i.e., precise height distribution of LER in the line pattern's sidewall) is beneficial for the evaluation of advanced devices with sidewall roughness dependent on height, 21 although special data processing is necessary. Tip scanning along a line pattern, as shown in Fig.…”

Diffusion mechanism of fluorine in plasma processing of III–V semiconductor compounds

“…[5][6][7] Recently, the fabrication of Fin-type transistors using compound materials has also been studied. [8][9][10][11] Considering Si gate processing, damage (i.e. Si recess) caused by plasma etching during mask processing deteriorates the device characteristics.…”