2019
DOI: 10.1016/j.jcrysgro.2018.12.014
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InAs/GaSb thin layers directly grown on nominal (0 0 1)-Si substrate by MOVPE for the fabrication of InAs FINFET

Abstract: We demonstrated the fabrication of a densely packed InAs fins network for nanoelectronic applications. High crystalline quality GaSb/InAs layers have been grown directly on 300 mm nominal (001)-Si substrate. The InAs was then processed by etching step using a lithographic mask based on block copolymer to obtain sub-20nm width fins. This block copolymer has been optimized to selfassemble into lamellar structure with a period of 30nm, standing perpendicular to the substrate thanks to a neutral layer. STEM-HAADF … Show more

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Cited by 3 publications
(2 citation statements)
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“…Low-crystalline-defect epitaxial layer growth by metalorganic chemical vapor deposition on Si(100) can be extended to other materials. ,, In this study, the top-down structure approach, based on Cl 2 /N 2 plasma etching, was applied with the optimized conditions on a GaSb layer. Figure c shows vertical GaSb nanowires on a Si(100) substrate with a length of 660 nm and a diameter of 50 nm, demonstrating the versatility of the approach and envisioning a possible cointegration of GaAs and GaSb vertical nanowires on the same standard Si(100) microelectronic substrate.…”
Section: Resultsmentioning
confidence: 99%
“…Low-crystalline-defect epitaxial layer growth by metalorganic chemical vapor deposition on Si(100) can be extended to other materials. ,, In this study, the top-down structure approach, based on Cl 2 /N 2 plasma etching, was applied with the optimized conditions on a GaSb layer. Figure c shows vertical GaSb nanowires on a Si(100) substrate with a length of 660 nm and a diameter of 50 nm, demonstrating the versatility of the approach and envisioning a possible cointegration of GaAs and GaSb vertical nanowires on the same standard Si(100) microelectronic substrate.…”
Section: Resultsmentioning
confidence: 99%
“…Additionally, by employing BCP self-assembly to manufacture FinFET nanodevices, the total processing cost and the number of process steps can be reduced by ~9.5 and 30%-40%, respectively. In a separate work, using templates made from the self-assembly of lamellar-forming PS-b-PMMA, InAs FinFET nanodevices with a 15-nm width fin have been prepared by Cerba et al (2019). Electrical measurements demonstrate that the drain currents of the 100-and 200-nm long InAs fins are 70 and 2 μA, respectively.…”
Section: Fin Field-effect Transistorsmentioning
confidence: 99%