In this article, the authors investigate the formation and removal of resist residues with the main objective to improve the reliability of transistor gate fabrication. Device performance is strongly dependent on the quality of metal contacts and the interface between gate metal and substrates. Reliable transistor fabrication becomes increasingly difficult as transistor dimensions shrink. Residual resist layers can become significant if wet or dry etching steps are required for gate recessing, e.g., for high electron mobility transistors or the removal of thin oxide layers in III-V metal oxide semiconductor field effect transistor fabrication. They observe two sorts of residual resist layers in polymethyl methacrylate (PMMA): exposed and nonexposed. Exposed residuals have been observed by many groups in electron beam exposed and developed regions of PMMA. In this article, they show that the observed granularity lies on top of a continuous residual film and consider this effect on gate fabrication. They also present evidence of a nonexposed residual layer observed in regions of unexposed resist which have been subject to a standard solvent based resist strip and cleaning procedure. They further demonstrate that CV measurement techniques can be used to detect the presence of residual layers of resist.

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Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.

To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) [1] to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. For ultimate CMOS exploitation, self-aligned III-V MOSFETs with sub-20 nm critical dimensions will have to be realized using silicon compatible process flows. This paper reviews the current status of III-V MOSFET research from the perspective of silicon ULSI process compatibility.