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To address issues associated with continual scaling of the International Technology Roadmap for Semiconductors (ITRS) [1] to follow Moore's Law, MOSFETs with high mobility channel materials are now being seriously considered. As a result, there has been a significant expansion in research into III-V MOSFETs as a potential n-channel device solution. For ultimate CMOS exploitation, self-aligned III-V MOSFETs with sub-20 nm critical dimensions will have to be realized using silicon compatible process flows. This paper reviews the current status of III-V MOSFET research from the perspective of silicon ULSI process compatibility.

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