The notch occurrence factor in polysilicon etching was investigated using a newly designed test mask pattern. This pattern varied the space width, the line width of the line-and-space structure, and the pad perimeter which connected the line-and-space structure. By using this test pattern, it was found that the notch depth increases as the “perimeter ratio”, (i.e. the ratio of the pad perimeter to the notch line perimeter), increases. Moreover, when the perimeter ratio was very small, the notch depth was quite small. Therefore, it is considered that the notch is caused by electron supply from the periphery of the pad which collects the electrons from plasma. As a result of this electron conduction, in the case of the non-connected lines, the notch occurs only outside the line of the line-and-space structure, and in the case of the connected lines, the notch occurs at all of the connected lines. The notch depth difference between the non-connected lines and connected lines is explained by the difference in perimeter ratio.

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This paper reports tri-gate sub-100 nm In 0.53 Ga 0.47 As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of g m,max > 1.5 mS/µm, at V DS = 0.5 V. This result is the best balance of g m,max and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ 0 = 760 cm 2 /V-s and peak v x0 = 1.6×10 7 cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.Introduction: Indium-rich InGaAs channel materials are a candidate for future low-power logic applications [1-2]. Tri-gate transistor architecture has been successfully demonstrated for improved electrostatics in Si MOSFETs [3][4] and most recently in III-V MOSFETs [5][6]. However, most of III-V tri-gate devices reported so far have shown wide fin geometry or poor interface quality between high-k dielectric and sidewall of etched Fin, failing to demonstrate performance and electrostatics benefit over the best ultrathin-body (UTB) planar III-V QW MOSFETs [7][8]. In this work, tri-gate In 0.53 Ga 0.47 As QW MOSFETs with bi-layer high-k dielectrics of Al 2 O 3 /HfO 2 are reported. In particular, L g = 60 nm tri-gate In 0.53 Ga 0.47 As QW MOSFETs with narrow fin width (W fin ) of 30 nm, fin height (H fin ) of 20 nm and EOT < 1 nm, yield excellent electrostatic integrity and performance benefit over UTB planar III-V MOSFETs, such as S = 77 mV/dec., DIBL = 10 mV/V, g m > 1.5 mS/µm and v ox = 1.6ⅹ10 7 cm/s. This result is significant because it shows that excellent electrostatics and performance can be achieved with high-k oxides directly on an etched tri-gate MOSFETs down to L g = 60 nm.

We demonstrated a coverage-controllable sidewall protective film by controlling the degree of oxidation during plasma-enhanced SiO2 atomic layer deposition (ALD) as a novel technology to suppress bowing in a high-aspect-ratio-contact (HARC) hole etch process. By depositing SiO2 protective film with atomic order on only the top-local region of patterns, to suppress bowing was achieved during HARC etch without the shrinkage of the bottom critical dimension (CD) and etch-stop. In addition, we investigated the parameters that determine the ALD coverage to estimate the coverage profile of sidewall protective film. By analyzing the relationship between activation time and ALD film thickness at each AR, we confirmed that the coverage is determined by the transport of oxygen radical based on the Knudsen transport model. Furthermore, we developed an ALD simulator from the transport model, and successfully estimated the coverage of protective film during etching to improve the verticality of the HARC profile with small bowing-bottom CD bias.

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