Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on the Intel R Architecture (IA) ISA, a lot of attention has been given to translating IA to other ISAs. The recent trends in industry for both smaller ultra-mobile PCs and more powerful embedded and mobile internet devices (e.g. smartphones) are blurring the frontiers between these distinct markets. As a result, this market convergence is creating great interest in DBT from ISAs that currently dominate the embedded and mobile-internet-device markets (e.g. ARM, MIPS, and PowerPC) to IA. This paper investigates the main challenges that arise when targeting IA in a DBT. We identify the two key issues in efficiently translating from other ISAs to IA: IA's small number of registers, and its condition-code handling mechanism. To address these issues, we propose a combination of software and hardware solutions. Although motivated by IA, these techniques are not IA-specific, and they can be applied to other architectures with similar limitations to make them better DBT-targets. We have prototyped these techniques in Harmonia, an ARM-to-IA DBT tool based on open-source QEMU. Our experiments show that Harmonia achieves an average of 55% (up to 164%) of the performance of highly optimized native binaries, and an average speedup of 2.2× on top of the baseline QEMU.