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Various metals with different galvanic potentials are used to fabricate the microelectronic circuits. One of the most commonly used processes during integrated circuit manufacturing is the tungsten via fill. To obtain maximum interconnect density with low via resistance requires that metal-via overlap is essentially zero. Zero overlap with litho variations and thus misalignment may result in unlanded vias. Since the vias are used to connect various metal levels, a large number of these cases may occur causing device failures and thus yield loss. To study this problem a variety of test structures were studied and a new mechanism of corrosion was found. The tungsten corrosion observed in these structures was found to be photo-induced. In this paper we will discuss the mechanism of photoinduced galvanic corrosion that occurs between the aluminum and tungsten metal layers during microelectronic manufacturing.

During the transfer of an 80V 0.35µm based technology (I3T80U) developed at AMI Semiconductor from the mother fab to a second fab, field transistor biased-temperature instability (BTI) failures were encountered. The polarity of the degradation in the field transistor threshold voltage does not indicate a mobile ion problem. Also, the behavior does not follow a typical signature of traps at the silicon-oxide interface. The degradation model will be shown. The proposed mechanism is the presence of a residual film. Simulation results of the proposed mechanism, as well as a manufacturing solution for these failures is explained in this paper.

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