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Sparse matrix-vector multiplication (SpMV) is a fundamental operation for many applications. Many studies have been done to implement the SpMV on different platforms, while few work focused on the very large scale datasets with millions of dimensions. This paper addresses the challenges of implementing large scale SpMV with FPGA and GPU in the application of web link graph analysis. In the FPGA implementation, we designed the task partition and memory hierarchy according to the analysis of datasets scale and their access pattern. In the GPU implementation, we designed a fast and scalable SpMV routine with three passes, using a modified Compressed Sparse Row format. Results show that FPGA and GPU implementation achieves about 29x and 30x speedup on a StratixII EP2S180 FPGA and Radeon 5870 Graphic Card respectively compared with a Phenom 9550 CPU.

Reliable detection of appliance state change is a barrier to the scalability of Non Intrusive Load Monitoring (NILM) beyond a small number of sufficiently distinct and large loads. We advocate a hybrid approach where a NILM algorithm is assisted by ultra-low-cost outlet-level sensors optimized for detecting appliance state change and communicating the event on a best-effort basis to a central entity for opportunistic fusion with the state change detection mechanism within NILM. In support of such an approach we present the implementation of an appliance power state sensor which achieves low cost via design choices such as a transmit-only radio. We also present results from a study where the sensors tracked power states of tens of appliances with high accuracy.

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