Abstract. In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF (3 6m ) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF (3 m ). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

RFID-tags are a new generation of bar-codes with added functionality. An emerging application is the use of RFIDtags for anti-counterfeiting by embedding them into a product. Public-key cryptography (PKC) offers an attractive solution to the counterfeiting problem but whether a publickey cryptosystem can be implemented on an RFID tag or not remains unclear. In this paper, we investigate which PKCbased identification protocols are useful for these anticounterfeiting applications. We also discuss the feasibility of identification protocols based on Elliptic Curve Cryptography (ECC)

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Abstract. In this paper algorithms and architectures for new GF (3 m ) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components.