UML2 and SysML try to adopt techniques known from software development to systems engineering. However, the focus has been put on modeling aspects until now and quantitative performance analysis is not adequately taken into account in early design stages of the system. In this paper, we present our approach for formal and simulation based performance analysis of systems specified with UML2/SysML. The basis of our analysis approach is the detection of communication that synchronize the control flow of the corresponding instances of the system and make the relationship explicit. Using this knowledge, we are able to determine a global timing behavior and violations of this effected by preset constraints. Hence, it is also possible to detect potential conflicts on shared communication resources if a specification of the target architecture is given. With these information it is possible to evaluate system models at an early design stage.

In this paper, we present a novel approach for a region-based extension for a fully adaptive and fault-tolerant routing algorithm for Network-on-Chips (NoCs) called ForceDirected Wormhole Routing (FDWR) [1]. The proposed extension for the FDWR reduces the size of the routingtable of a switch and therefore the hardware costs. Despite the region-based extension the FDWR can be used for different NoC topologies like mesh, torus, and hypercube. The region-based extension is integrated into the Transaction Level Model (TLM) of the switch. We show how the proposed extension for the FDWR reduces the size of the routingtable. Simulation results depict that the traffic is distributed uniformly across the entire network despite the region-based extension. Furthermore, it is shown that in case of faulty switches the area around that switches is not overloaded and that the traffic is uniformly distributed across the entire network.

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