In this work, we analyze compensating defects which are formed after implantation of aluminum (Al) into n-type 4H-SiC epitaxial layers and subsequent thermal annealing. These defects reduce the expected free charge carrier density by 84% for a low doped layer with [Al]impl≈ 9ž·1016cm-3and by 27 % for a high doped layer with [Al]impl≈ 2·ž1019cm-3. Furthermore, an electrical activation ratio of implanted aluminum ions of 100 % is calculated. The ionization energy of implanted aluminum as measured by Hall effect and admittance spectroscopy ranges from 101 meV to 305 meV depending on the doping concentration.

Germanium (Ge) doping of 4H silicon carbide (SiC) has recently attracted attention because a conductivity-enhancing effect was reported. In this work, we report on an experimental and theoretical approach to elucidate this effect. Ge and tin (Sn) – a second candidate of group IV elements – have been implanted into n-type 4H-SiC. Despite the expected isoelectric nature of Ge and Sn, a more efficient annealing of implantation-induced defects was observed compared to noble gas implantation with identical simulated initial implantation damage. In particular, a strong reduction of the prominent Z1/2 defect was observed. Density functional theory calculations under equilibrium conditions show that Ge is mainly incorporated on a substitutional silicon lattice site without creating new charge transition levels in the bandgap. The low abundance of other Ge-related defects suggests that kinetic mechanisms should be responsible for the observed effect of group IV doping.

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In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions.