Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride layers were deposited on Si substrates by an atomic-layer-deposition (ALD) technique at low temperatures (<550 °C). The interface state density at the ALD silicon nitride/Si-substrate interface was almost the same as that of the gate SiO2. No hysteresis was observed in the gate capacitance–gate voltage characteristics. The gate leakage current was the level comparable with that through SiO2 of the same Teq. The conduction mechanism of the leakage current was investigated and was found to be the direct tunneling. The ALD technique allows us to fabricate an extremely thin, very uniform silicon nitride layer with atomic-scale control for the near-future gate dielectrics.

Extremely thin (equivalent oxide thickness, Teq=1.2 nm) silicon-nitride high-k (εr=7.2) gate dielectrics have been formed at low temperatures (⩽550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface.

Growth and electrical properties of atomic-layer deposited ZrO 2 / Si -nitride stack gate dielectrics J. Appl. Phys. 95, 536 (2004); 10.1063/1.1629773Atomic layer deposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing ZrO 2 thin films for gate dielectrics have been formed at low temperatures ͑200°C͒ by an atomic-layer deposition ͑ALD͒ technique using Zr(t-OC 4 H 9 ) 4 and H 2 O source gases. An ultrathin ͑physical thickness T phy of ϳ0.5 nm͒ Si nitride layer was deposited on a Si substrate by ALD before the deposition of ZrO 2 . Transmission electron microscopy showed that the Si nitride barrier layer successfully suppressed the formation of a SiO 2 interfacial layer. Because of the extremely uniform thickness control capability in the ultrathin region and the low thermal budget of the ALD process, the ALD process for the ZrO 2 /Si nitride stack structure is a promising candidate for fabricating the ultrathin gate dielectrics for sub-0.1-m complementary metal-oxide-semiconductor transistors.

Thin (equivalent oxide thickness Teq of 2.4 nm) silicon nitride was deposited on Si substrates by atomic-layer deposition (ALD) at low temperatures (<550 °C). Substantial enhancement of reliability was obtained with respect to the conventional SiO2 samples. An exciting feature of suppressed soft breakdown events was observed. Injected-carrier-induced physical damage, which results in the formation of the conductive filaments at the poly-Si/ALD-Si-nitride and ALD-Si-nitride/Si-substrate interfaces, is suppressed due to the higher stability of the Si–N bonds than that of the strained Si–O bonds. This suppression of physical damage leads to enhanced reliability. Therefore, the ALD silicon nitride can be a good choice for a highly reliable ultrathin gate dielectric in deep submicron complementary metal–oxide–semiconductor technology.

Narrow ͑у95 nm͒ and extremely thin ͑ϳ7 nm͒ heavily phosphorous-doped polycrystalline-silicon ͑poly-Si͒ wires were fabricated by low-pressure chemical vapor deposition. The electrical conduction mechanism has been investigated at low temperatures ͑down to ϳ5 K͒, and observation by transmission electron microscopy ͑TEM͒ was carried out. Single-electron effects such as Coulomb oscillations have been observed at temperatures up to 80 K. The size of the island in the poly-Si wires was estimated from the electrical properties, and it was in the same order as the grain size of the poly-Si measured by TEM. A maximum tunnel barrier height of ϳ26 meV of the poly-Si grain boundary is obtained from the temperature dependence of the conductance of the sample. A model for the electronic conduction through multiple islands was proposed from the width dependence of their electrical properties.