When Cu wafers are exposed to H 2 /N 2 plasma, hillocks are formed on the Cu wafer surface by a plasma cleaner with a surface wave plasma source. Plasma cleaning is divided into the initial stage and the rising temperature stage. Under a supply of H 2 /N 2 gas and with the plasma power turned on, the H radicals first restore native copper oxide to pure copper. The N radicals then compete with the H radicals, and diffuse to the Cu grain boundary, which is the initial stage. During the rising temperature stage, plasma energy is absorbed by the Cu surface, and the wafer temperature increases rapidly. Consequently, plasma-enhanced compressive stress leads to the formation of Cu hillocks. For a plasma with a higher N/H radical ratio, more N radicals diffusing to the Cu grain boundary results in more Cu-N compounds, which make up the main source of stress during H 2 /N 2 plasma cleaning. Experimental results indicate that using a plasma cleaner with an inductively coupled plasma source can achieve a lower N/H radical ratio, thus avoiding the formation of Cu hillocks.The Cu dual damascene process has been widely employed for fabricating multilevel interconnection schemes in ultralarge scale integration ͑ULSI͒ circuits. This is because Cu dual damascene wiring provides significant advantages over the conventional Al metallization process. Therefore, many issues related to this process have been studied in detail. 1-5 Some of these issues affect the yield of the via chain. 4-6 The first via approach for the dual damascene structure consists of the following sequence. ͑i͒ Via etching through the whole dielectric stack (trench ϩ via), and then bottom antireflective coating ͑BARC͒ via filling, (ii) trench lithography, (iii) BARC etch back, (iv) trench etching in fluorinated silicate glass ͑FSG͒, and then O 2 -based plasma cleaning, and (v) capping nitride removal, and then O 2 -based plasma cleaning. The schematic process is shown in Fig. 1. Sometimes, it is difficult to stop the etch on the thin nitride film during via etching due to low or unstable oxide/nitride selectivity. Therefore, the Cu underlayer will be exposed to air after via etching. Moreover, it is observed that using only wet solvent cleaning after nitride removal will result in some residue, as shown in Fig. 2. Therefore, it is also necessary to use plasma cleaning after nitride removal. For conventional postetch cleaning technology used in the Al interconnection process, most recipes use O 2 -based plasma with high temperatures of 250-275°C. Even though the Al underlayer is exposed to air after via or trench etching, it is notable that the thin Al 2 O 3 compound on Al surfaces is not oxidized continuously during O 2 -based plasma cleaning. However, the weak Cu oxide on the Cu surface cannot provide an effective barrier to prevent Cu bulk from continuous oxidization at high temperature. These copper oxides may possibly cause difficulty in subsequent cleaning and reduction in interconnection yield. Therefore developing a new dry cleaning technology for Cu dual...

Copper ͑Cu͒ contamination at the wafer bevel, back side surface, and exclusion zone is identified step-by-step following a typical dual-damascene process. The shield ring of a physical vapor deposition system does not protect the exclusion zone and bevel efficiently. Also, Cu may dissolve and accumulate in the solvent used for post dielectric etch clean. Dissolved Cu atoms may then redeposit on the wafer surface. Furthermore, the rough back side surface traps Cu atoms easier than the smooth front side surface. If there is no SiO 2 film on the back side surface, post chemical mechanical polish cleaning using dilute HF cannot remove Cu at the back side surface. An optimized single-wafer spin-etch process was proposed. An optimal etchant consisting of HF, HNO 3 , H 2 SO 4 , and H 3 PO 4 with ratios 0.5:3:1:0.5 showed excellent performance. Experiments demonstrated that a very short, 10 s, back side clean can totally remove Cu from back side surface, bevel, and 2 mm exclusion zone. A ''wafer shift'' procedure was also proposed to solve the pinmark issue near the edge pin due to etchant remnant. The optimized cleaning technique shows shorter process time and higher cleaning efficiency than those reported previously.With the progress of integrated circuit ͑IC͒ processing technology, the feature size is scaled down continuously. As the device performance and the circuit density are improved due to shorter channel length and smaller device geometry, the resistance and capacitance of multilevel interconnects are increased due to the thinner and longer metal wires and the narrower space between them. Copper ͑Cu͒ has been recognized as the most suitable alternative for aluminum as an interconnect material because of its low electrical resistivity and excellent electromigration resistance.

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device.

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In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts.