In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.

In this paper, a new column-parallel analog readout architecture, which is composed of a high-gain amplifier, a forward noise-canceling circuitry (FNC), and sample-and-hold (S/H) capacitors, has been presented for low-noise CMOS image sensors (CIS). A FNC has been proposed to provide a sharp noise-filtering for high-frequency noise arising from the readout signal chain, which effectively reduces random noise of the pixel source follower and column amplifier. In order to keep the high-sensitivity and high-dynamic range output, dual-gain readout chains have been adopted. A prototype 400H × 250V CIS using the readout architecture with the FNC was fabricated in a 0.18 µm 1-poly 3-metal CMOS process with pinned-photodiodes. The experimental results revealed the input-referred noise of the proposed readout architecture was 65 µVrms, which has been reduced by 24% compared to that of the conventional readout architecture.

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