Intel, Haifa, IsraelWith the introduction of mobile laptop platforms into the wireless communication market, the usage of WiFi in everyday life has taken off exponentially. Further penetration into additional platforms and products, such as handheld devices and PDAs, requires a dramatic reduction in cost and smaller form factors of the wireless device. This can only be achieved by higher levels of component integration onto the Silicon radio chips.Until now, there have been a wide variety of features on radio chips deployed in WiFi platforms. For example, radio chips integrating 1×2 [1] and 2×2 [2] MIMO transceivers have been presented. A single-chip solution has been presented in [3], integrating both MAC and radio, but with off-chip power amplifier (PA) and low-noise amplifiers (LNA). On-chip integration of both LNA and Class-A PA has been presented, supporting only 802.11g protocol [4]. Finally, a radio chip that integrates LNA and PA for the 802.11a protocol has been reported in [5], however, it requires offchip (on board) components, such as matching and load elements, which increase the cost and size of the solution.This paper presents preliminary results of a radio chip design, implemented in a standard 90nm CMOS process, which provides significant platform cost reduction by fully integrating the LNAs and high efficiency Class-AB PAs (and their matching networks) in a 1×2 scheme for 802.11a/g/n protocols.The block diagram of the radio architecture is presented in Fig. 20.1.1. The chip contains two RF sections. Each consists of two RX chains (one for each band) including an LNA, but a single TX chain with an integrated PA. The TX chain of the first RF section operates in 2.4-to-2.5GHz band, while that of the second section operates in 5-to-6GHz band. This radio is based on a zero-IF direct-conversion technique. The topology uses a shared passive mixer for RX/TX and a shared baseband (BB) filter. Moreover, the gain of the TX and RX chains are digitally programmable. The radio includes a fractional-N synthesizer using a 40MHz reference clock. It features 20μs lock-time mechanism (for fast channel scan) and low integrated phase noise of less than −44dBc and −38dBc for the low and high bands, respectively. Finally, the LO frequency plan uses a 3/4 and 3/2 multiplication of the synthesizer output frequency for the low and high band chains, respectively.The RX chains are composed of two triple-cascode LNAs, presented in Fig. 20.1.2, passive mixers and a five-pole BB filter. In the 2.5GHz band, the LNA uses an embedded single-to-differential converter, in order to eliminate the off-chip balun. The gain imbalance measured by a high impedance probe at the output of the 2.5GHz LNA is less than 1dB. Due to the higher sensitivity to common-mode noise and package parasitics, a fully differential topology is used for the 5-to-6GHz LNA. Both LNAs include 4 steps of gain control using a current steering mechanism (see Fig. 20.1.2). The total gain of both chains can be varied from 64dB to −6dB in 1.5dB steps. The overall m...
