An active feedback network-based bandwidth extension technique for CMOS differential transimpedance amplifier (TIA) is proposed in 0.18 µm CMOS process technology. The design consists of three stages in differential mode. The first stage is a common-source amplifier that minimizes noise. A common collector stage is used for level shifting and buffering in the second stage. The third stage is a differential amplifier that provides additional gain. In addition to these three stages, an active CMOS negative feedback circuit is used for extending the bandwidth. The proposed design achieves a gain of 45.2 dBΩ with a 3 dB bandwidth of 21.23 GHz. The active feedback circuit provides an additional bandwidth of 7.3 GHz. The TIA achieves a data rate of 30 Gb/s with input-referred noise current density of 63.1 pA/ Hz and jitter of 9.07 ps. The TIA consumes a power of 10.3 mW with a supply voltage of 1.8 V.

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