Double patterning (double exposure and double etch) is definitely a viable solution for overcoming the physical resolution limit of k1=0.25 of imaging systems. This article presents the overlay budget for a double patterning technique using a 45nm technology node flash memory device with k1∼0.20 and 193nm dry lithography. Adopting double exposure, the final pattern is composed of two lithography patterns within the resolution capability of the exposure tool and then combined with the double etching processes. The photoetch photoetch approach creates the overlay between the two exposures which is the most critical issue to be addressed. This article presents the adopted scanner setup, mask requirements, and efficient overlay metrology setup in order to achieve the overlay roadmap of 6nm for the 45nm technology node.

Double patterning is the best technique which allows 193nm immersion lithography to anticipate the 32 nm node, before EUV lithography. The final device pattern is formed by two independent patterning steps where the dense pitch is doubled. This allows printing each patterning step with higher k1 imaging factor.In this paper we present the overlay and CD budget applied to a double patterning (DP) technique for the definition of a 32nm technology node device, using an immersion scanner tool. A balance among different factors which affects the final CD of the device is necessary to optimize the imaging and the alignment performances of the exposure tool. A preliminary activity is also necessary to choose the most suitable mask splitting strategy. Adopting a single mask, which is exposed twice with the appropriate shift -the final pitch -, makes the overlay between the two exposures less critical than splitting the complementary layouts on two different masks. Finally, the CD uniformity of the pooled distributions from the two exposures is evaluated in order to define the requested tool performances in terms of overlay, CD control and metrology.

Current 90nm Flash memory design introduces imaging critical points in several devices levels: active, poly, contacts, and first metallization. Among standard Resolution Enhancement Techniques (RET), Off-axis illuminations play a fundamental role, because they are capable of providing better imaging contrast and improved process latitude in low K 1 regime with very dense structures. Starting from the simulation study of real device layer geometries, object of this work is to propose a solution in terms of illumination schemes and mask choice (binary or halftone) for each critical layer, considering K 1 around 0.35 in ArF lithography. Dedicated off-axis illuminations will be compared to standard illumination modes, underlining the benefits in terms of ultimate resolution, process window and line edge roughness improvement. Experimental data confirmed the predicted gain in process robustness and, as expected, showed great line edge roughness improvement and less marginality to pattern collapse.

The laser bandwidth and the wavelength stability are among the important factors contributing to the CD Uniformity budget for a 45 nm and 32nm technology node NV Memory. Longitudinal chromatic aberrations are also minimized by lens designers to reduce the contrast loss among different patterns. In this work, the residual effect of laser bandwidth and wavelength stability are investigated and quantified for a critical DOF layer. Besides the typical CD implications we evaluate the "image placement error" (IPE) affecting specific asymmetric patterns in the device layout. We show that the IPE of asymmetric device patterns can be sensitive to laser bandwidth, potentially resulting in nanometer-level errors in overlay. These effects are compared to the relative impact of other parameters that define the contrast of the lithography image for the 45nm node. We extend the discussion of the contributions to IPE and their relative importance in the 32 nm double-patterning overlay budget.

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