The nursing outcomes of hospitalized patients whose plans of care include death anxiety, which is a diagnosis among patients at the end-of-life, are obscure. The authors of the current article applied data mining techniques to nursing plan-of-care data for patients diagnosed with death anxiety, as defined by North American Nursing Diagnosis Association International, from four different hospitals to examine nursing care outcomes and associated factors. Results indicate that <50% of patients met the expected outcome of comfortable death. Gerontology unit patients were more likely to meet the expected outcome than patients from other unit types, although results were not statistically significant. Younger patients (i.e., age <65) had a lower chance of meeting the outcome compared with older patients (i.e., age ≥65) (χ2(1) = 9.266, p < 0.004). Longer stays improved the chances of meeting the outcome (χ2(2) = 6.47, p < 0.04). Results indicate that death anxiety outcomes are suboptimal and suggest the need to better educate clinicians about diagnosing and treating death anxiety among patients who face the end-of-life transition.

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Energy efficiency is a crucial problem in data centers where big data is generally represented by directed or undirected graphs. Analysis of this big data graph is challenging due to volume and velocity of the data as well as irregular memory access patterns. Graph sampling is one of the most effective ways to reduce the size of graph while maintaining crucial characteristics. In this paper we present design and implementation of an FPGA based graph sampling method which is both time-and energy-efficient. This is in contrast to existing parallel approaches which include memory-distributed clusters, multicore and GPUs. Our strategy utilizes a novel graph data structure, that we call COPRA that allows timeand memory-efficient representation of graphs suitable for reconfigurable hardware such as FPGAs. Our experiments show that our proposed techniques are 2x faster and 3x more energy efficient as compared to serial CPU version of the algorithm. We further show that our proposed techniques give comparable speedups to GPU and multi-threaded CPU architecture while energy consumption is 10x less than GPU and 2x less than CPU.

This paper proposes a novel FPGA-based accelerator for the memory and compute-intense re-gridding process used in computation of Non-uniform Fast Fourier Transform (NuFFT). The re-gridding process interpolates arbitrary sampled data onto a uniform grid using an interpolation kernel function. This regridding step is considered one of the most time consuming step in entire NuFFT computation. We propose a memory-efficient technique based on the novel use of customizable hardware components such as FPGA block memory in First-In-FirstOut (FIFO) configuration, fill-rate based arbiter, distributed RAM and an array of pipelined single precision floating point multipliers and adders. The proposed architecture exhibits high performance over a wide range of configurations and datasizes. A speed-up of over 9.6 was achieved when compared with existing FPGA-based technique at a 7 times higher MFLOPS per watt. Compared to GPU based technique, over 6 times higher MFLOPS per watts were achieved.

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