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An exclusive-OR transform of input variables signaficantly reduces the size of the P L A implementation f o r adder and comparator circuits. For n bat adder circuits, the size of P L A for transformed functions is O ( n 2 ) . In comparison, when the complete truth-table of an adder is minimized, the P L A size will be 0(2n+2). Similarly, for an n bit comparator, the size of the P L A is reduced from 0(2n+1) to O(n). These implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates.

Anand Pande* Broadcom IndiaA number of DSP algorithms involve linear transforms employing weighted sum computations, where the weights are fixed at design time. Add-shvt implementation of such a computation results in a Data Flow Graph that has multiple precision variables and functional units. We explore the potential of precision sensitive approach for the high level synthesis of such multi-precision DFGs. We focus on fixed latency implementation of these DFGs.We present register allocation, functional unit binding and scheduling algorithms to exploit the multi-precision nature of such DFGs for area efficient implementation. The proposed approach is fairly generic and could be applied to multiprecision DFGs involving any type of functional units. Signijkant improvements of upto 27% have been obtained over the conventional high-level synthesis approach.

This pqer describes two logic minimization algorithms. CAMP (Co'mputer Aided Miaimization Procedure) minimizes single functious. The mintenns are covered either by essential prime implicaots or by selective prime implicants. The two types of prime implicants are determined one at a time tbus completely avoiding the computationally expensive covering problem. The adjacency of a mintene, that depends upon the proximity of this minterm witb respect to other minterms on the Karnaugh map, guides the determiaation of prime imp&ants. This procedure is nonheu,ristic and has proved to be very efficient for large number of input variables. The multiple output minimization (MOM) algorithm generates the product terms with maximum sharing between the output fuactioas. In addition to using adjacency, this procedure is also guided by the frequency with which a misterm is used by the functions. Examples show the performance of tbis algorithm to be equal or better thaa many other minimization procedures.

The feasibility of generating high quality functional test vectors f o r sequential circuits using the Growth (G) and Disappearance ( 0 ) fault model has been demonstrated earlier. In this paper we provide a theoretical validation of the G and D fault model by proving the ability of this model to guarantee complete stuck fault coverage an combinational and sequential circuits synthesized employing algebraic transformations. W e also provide experimental results o n a wide range of synthesized FSMs. A comparison with a state-of-the-art gate level ATPG tool demonstrates the eficiency and limitation of the functional approach.