Analog macromodeling of capacitive coupling faults in digital circuit interconnects

Sathe, A.; Bushnell, M.L.; Agrawal, V.D.

doi:10.1109/test.2002.1041781

Cited by 15 publications

(5 citation statements)

References 17 publications

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“…Let us comment on the runtime of the proposed method to the runtimes of the tools using layout information in [10] and [11]. It is difficult to compare our experimental results to the experimental results in [10] and [11] fairly, because the tools in [10] and [11] were applied to only combinational circuits.…”

Section: Practical Testing and Experimental Runtimesmentioning

confidence: 99%

“…It is difficult to compare our experimental results to the experimental results in [10] and [11] fairly, because the tools in [10] and [11] were applied to only combinational circuits. Though neither provides the runtime information, we believe that the runtimes of our method are substantially shorter than those of the tools in [10] and [11]. We justify this based on the fact that the tools developed in both were applied only to small circuits.…”

Section: Practical Testing and Experimental Runtimesmentioning

confidence: 99%

“…This paper is an expansion of the work presented in [9], and it contains fewer constraints and more experimental results. Two other methods [10], [11] have been proposed following our work presented at the 2001 International Test Conference [9]. In [10], a crosstalk target identification framework was proposed that is composed of a set of extractors and filters which together identify the target faults.…”

Section: Introductionmentioning

confidence: 99%

“…In [10], a crosstalk target identification framework was proposed that is composed of a set of extractors and filters which together identify the target faults. In [11], a capacitive coupling fault model and a crosstalk candidate reduction algorithm is proposed. Both these methods rely heavily on the layout information and are computationally expensive.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi

Keller

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.Index Terms-Crosstalk faults, lists of the target crosstalk faults, synchronous sequential circuits.

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Section: Practical Testing and Experimental Runtimesmentioning

confidence: 99%

Section: Practical Testing and Experimental Runtimesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi

Keller

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Following this work, a pruning method was proposed in [5] for crosstalk target identification in sequential circuits. A different method was proposed in [6] to prune redundant crosstalk faults in sequential and combinational circuits. Unfortunately, none of these techniques address the problem of how to utilize the filtering resources in a costeffective manner.…”

Section: Introductionmentioning

confidence: 99%