Charge carrier transport in chemical vapor-deposited amorphous SiC/p-type crystalline Si heterostructures has been studied over the temperature range 80–400 K, using current–voltage (I–V), current–temperature (I–T), capacitance–voltage (C–V), and capacitance relaxation (C–t) characteristics. These heterojunctions exhibit high breakdown voltages (230 V) and a diode rectification ratio of 103 at ±0.5 V. At low temperatures (80–120 K) the a-SiC behaves like a dielectric, and the interface built-in voltage can be determined from the capacitance–voltage plot. The corresponding low forward bias current flow is limited by variable-range electron hopping conductivity at Fermi level in the a-SiC layer. At increasing temperature and forward bias voltage, an additional hole current component is found with the transport governed by a multistep tunneling hole emission process through the a-SiC/c-Si heterobarrier. At still higher forward bias voltages (>0.8 V), space-charge-limited hole conduction in the presence of traps in the a-SiC bulk limits transport.

The effect of high‐temperature treatments in inert atmosphere, performed after deposition of phosphorus‐doped polycrystalline silicon, on the accumulation of radiation‐induced charge in Si*SiO2Si structures is investigated. It is shown that these treatments lead to an increase of hole trap concentration on both SiO2 interfaces, and the hole trap creation at the Si*SiO2 interface is related with phosphorus diffusion from Si* into SiO2. A model of charge accumulation at the Si*SiO2 interface is proposed, which satisfactorily explains experimental data.

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An isothermal DLTS (I‐DLTS) method is proposed where the transient capacitance signal from the structure under study (MIS, p‐n or Schottky diodes) is measured at two times, with the interval between them successively changing from cycle‐to‐cycle of the periodically repeated processes. Parameters of deep levels are determined from the time positions and amplitudes of the I‐DLTS peaks recorded at several fixed temperatures. The I‐DLTS method provides more accurate correlation betweendeep level parameters with measured temperature and is less time consuming.

In the paper a measurement technique for study main technical and physical parameters of nanocluster non-volatile memory capacitance cell is presented. The charging/discharging process features associated with nanoclusters (nanocrystals) incorporated into gate dielectric are discussed. Original equipment for fast capacitance measurements based on computer interfaces is considers.