The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today"s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces the longterm reliability of circuits due to temperature-induced accelerated device and interconnects aging processes, and increases the cooling and packaging costs of these circuits. In this paper the main aim is to reduce power dissipation. A new design method for various logical circuits design, which is low power, compared to general Static CMOS logic. In this technique both NMOS transistor and PMOS transistors in various logic circuits is split into two transistors. Leakage current flowing through the NMOS transistor stack reduces due to the increase in the source to substrate voltage in the top NMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor Leakage current flowing through the PMOS transistor stack reduces due to the increase in the source to substrate voltage in the top PMOS transistor and also due to an increase in the drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for schematic simulation. The simulation technology used is MOSIS 180nm.

This paper describes a 0.5 jLm BiCMOS technology for high performance logic and SRAM's which is capable of supporting 5 V "hot carrier hard" circuit designs. In these designs the maximum drain-to-source voltage across a 0.5 jLm NMOS device is restricted to 4 V to ensure hot carrier reliability using 12 nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5 V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 picosee/picoFarad which is 30% smaller than the load drive factor for the same basic design gate built using an O.S jLm proceS8 with 20 nm gate oxide. The paper also discusses how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5 jLm BiCMOS process. The addition of these components permits a 23 jLm2 stacked 6-T CMOS SRAM cell to be realized, suitable for 4Mbit-clas8 BiCMOS SRAM's.