No abstract

A key issue in proceeding the digitization of Phase-Locked Loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for Time-to-Digital Converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter.

No abstract

Frequency synthesizers, and especially phase locked loops (PLL), are fundamental blocks used in every RF wireless application. Continuous demand for high levels of integration and reduced power consumption can only be realistically achieved using a digital control system approach. One of the most critical blocks in a digital PLL design is the digitally-controlled oscillator (DCO). The function of a DCO is to generate a signal whose frequency is proportional to a digital word calculated by a digital loop filter.DCOs for several communication standards have been analyzed in the literature [1,2,3,4,5] but none of them is suitable for the frequency division duplexing mode of UMTS because of the low power consumption required and the wide bandwidth of the output signal. If direct modulation of the RF signal is targeted, an extremely wide fine-tuning range is required. System simulations show that a fine-tuning range on the order of 100MHz is needed to achieve modulation. The approaches shown in [1], [2] based on ring oscillators, are not suitable for UMTS because they have large phase noise. The LC-oscillator-based DCOs described in [4] and [5] result in low phase noise, but their power consumption is too high for a continuously operating system. The solution presented in [3] has acceptable phase noise and low power consumption, but the fine-tuning range is not suitable to modulate a wideband signal. This paper presents the first fully digitally controlled oscillator suitable for UMTS applications implemented in a standard 0.13µm CMOS process with 6 metal layers. The oscillator has low power consumption and a wide fine-tuning range. For an output frequency of 2GHz, the system draws only 3.2mA in TX mode and 2.6mA in RX mode from a 2.5V supply, with a phase noise of -118dBc/Hz in TX mode and -115dBc/Hz in RX mode, both at 1 MHz offset. A wide course-tuning range, from 3.45 to 4.45GHz, is needed to cover all UMTS bands and is achieved using a binary-weighted switched capacitor bank. A wide fine-tuning range of more than 100MHz with discrete finefrequency steps of 200kHz maximum is achieved by a thermometer-coded varactor bank. Figure 11.10.1 summarizes all the points described above. According to this comparison, the DCO presented here has significantly smaller chip area and a wider fine-tuning range, which put this work well beyond the current state of the art. All these characteristics enable the realization of a fully digital phase path for a polar transmitter.The complete schematic of the DCO is shown in Fig. 11.10.2. Cross-coupled transistors M 1 and M 2 provide the negative resistance necessary to compensate the losses in the LC tank and sustain oscillations. The LC tank consists of a switchable binaryweighted capacitor bank and a thermometer-coded varactor bank in parallel with an inductor. The binary-weighted capacitor bank is used to achieve the coarse-frequency tuning range necessary to cover all the UMTS bands and is implemented with eight pairs of metal-insulator-metal capacitors connected in series through ...

No abstract