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Abstract-The I/Q imbalance is one of the performance bot tlenecks in transceivers with stringent requirements imposed by applications such as 802.11a. The mismatch between the frequency responses of two analog low-pass filters, used, e.g., for channel selection in zero-IF receivers, makes this I/Q imbalance frequency dependent. Usually, frequency-dependent I/Q mismatch is esti mated and corrected by adaptive techniques, which are complex to implement and may converge slowly due to noise. In this work, a simple, delay-based I/Q compensation scheme is proposed based on an extensive statistical analysis. Its digital implementation uses only two coefficients, which are tuned by a one-step two-tone error estimation. Simulations show that this hardware-efficient scheme significantly reduces the I/Q imbalance. Fig. 1. Usually, the RX chain in cludes an antenna (A), a low-noise amplifier (LNA), a pair of mixers driven by quadrature local-oscillator (LO) signals I ( ) and Q ( ), a pair of real low-pass filters (LPFs), a pair of analog-to-digital converters (ADCs) sampled at , and a digital signal processor (DSP) [3]. An orthogonal frequency-division multiplexing (OFDM) DSP, used in 802.11a [4], inherently contains a fast-Fourier transform (FFT) block. A zero-IF transmitter (TX) chain starts with a DSP and is followed by a pair of digital-to-analog converters (DAC), a pair of LPFs, a mixer/LO block, a power amplifier (PA), and an antenna [3]. Index Terms-ComplexThe main contributors of the RX or TX chain's I/Q imbal ance 1 are the gain error ( ) of the mixers, the phase error ( ) in the LO signals, the gain ( ) and phase ( ) mismatch between the LPF's transfer functions, and, finally, the gain error ( ) between the data converters (ADCs in RX, DACs in TX). The I/Q imbalance contribution of gain and phase errors can be modeled as a two-input two-output linear network with some inter-coupling coefficients [5]. These simple models can be individually applied to each block of mixers/LO, LPFs,

A CMOS current mirror with lower than Vos(3a,) input voltage requirement is presented. It is shown that the structure can be modified to provide cascode-type output resistance for output voltages even lower than 2 Vns(sa,). The topology of the proposed current mirror allows low distortion operation from a single 1.5V supply, which makes it attractive for low-voltage applications.Introduction: The current mirror is one of the most important building blocks of analogue integrated circuits. Modern VLSI systems now operating from single 3.3V supplies and dropping, require high performance current mirrors that can operate with

Variation in the "on" resistance of a MOS sampling switch can introduce distortion into the front end of a switched-capacitorjfilter or analog-to-digital converte,: We review three methods commonly used to linearize the resistance of a MOS switch and propose a new technique that addresses their limitations. A practical inethodfor implementation is also suggested.