A method for reducing the variation in "on" resistance of a MOS sampling switch

Ong, A.; Prodanov, V.; Tarsia, M.

doi:10.1109/iscas.2000.857465

Cited by 21 publications

(8 citation statements)

References 4 publications

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“…Unfortunately, the on-resistance of the switch is varied with the switched voltage and dependent on the magnitude of control voltage [1]. In order to minimize the switch-on resistance, the bootstrapped switch technique and the switch control-voltage boosted technique have been proposed in literature [2][3][4]. The technique based on bootstrapped switch generates the constant gate-source voltage for the MOS switch to prevent the on-resistance effects.…”

Section: Circuit Descriptionmentioning

confidence: 99%

A current signal CMOS sample-and-hold circuit

Luangpol

Petchmaneelumka

Kamsri

et al. 2007

2007 International Conference on Control, Automation and Systems

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This article presents a current signal sample-and-hold (S/H) circuit using 0.5f.lm CMOS technology. A current minimum circuit is used to sample the input signal in place of a sampling switch used in the conventional S/H circuit. The current peak detector is used to hold the signal from the minimum circuit in the "hold" state. The proposed configuration is adopted effectively to cancel switch feedthrough error. The performances of the proposed circuit are demonstrated using the PSPICE analog simulation program. Simulation results show the sampling frequency up to 100MHz and high accuracy.

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Section: Circuit Descriptionmentioning

confidence: 99%

A current signal CMOS sample-and-hold circuit

Luangpol

Petchmaneelumka

Kamsri

et al. 2007

2007 International Conference on Control, Automation and Systems

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“…With the increased demand for high speed high resolution ADCs though, the conventional bootstrapped switch has reached its limitations in terms of sampling linearity, as well as turn-on/off times, especially when operating at full swing range. Several methods have been proposed to further improve linearity [2], [3], [4], [5], [6]. Although these methods can be helpful, they have either limited input bandwidth or introduce increased design complexity.…”

Section: Introductionmentioning

confidence: 99%

Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter

Ramkaj

Tavernier

Steyaert

2015

2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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This paper presents a novel bootstrapped switch to serve as an input frontend for high resolution ADCs operating in the GHz frequency range. The switch reduces the on-resistance value and keeps it constant, resulting in precise sampling of input signals and better tracking bandwidth. The proposed bootstrapped switch is designed and simulated in TSMC 28 nm Digital CMOS. Simulation results at 800 MSamples/s show an improved and relatively constant spurious-free dynamic range (SFDR) and total harmonic distortion (THD) up to an input frequency of 1.6 GHz, which makes it suitable for a TimeInterleaved configuration.

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“…Another technique to remove dependence of R on on the threshold voltage was based on bootstrapping the gate of the switch device to a value that includes the threshold voltage [19,21,22]. However, there are several disadvantages such as using a replica transistor to extract threshold voltage without considering the second-order effect and process variation, high power consumption by used op-am [19] and current variation [22].…”

Section: Introductionmentioning

confidence: 99%

“…However, there are several disadvantages such as using a replica transistor to extract threshold voltage without considering the second-order effect and process variation, high power consumption by used op-am [19] and current variation [22]. Therefore, it is difficult to compensate body effect completely, by these methods.…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sarafi

A’ain

Abbaszadeh

2015

Circuits Syst Signal Process

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Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 μm CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of −78.81 and −62.99 dB in 100 MS/s at V dd = 1 Volt and 50 MS/s at V dd = 0.8 V, respectively.

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A method for reducing the variation in "on" resistance of a MOS sampling switch

Cited by 21 publications

References 4 publications

A current signal CMOS sample-and-hold circuit

A current signal CMOS sample-and-hold circuit

Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

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