Laser tests performed on a prototype chip to validate new SEU-hardened storage cell designs revealed unexpected latch-up and single-event upset phenomena. The investigations that identified their location show the existence of a topology-dependent dual node upset mechanism. Design solutions are suggested to avoid its occurrence

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We report on single event upset (SEU) and single event latchup (SEL) sensitivities under irradiation by protons and heavy ions for a variety of non-hardened high density static random access memories (SRAMs) with sub-micron feature sizes. The results are compared with previously measured sensitivities for similar devices with larger features. We discuss the sensitivity trends with temperature and examine other effects such as stuck bits.0-7803-8127-0/03/$17.00 (C) 2003 IEEE

The SEU hardness of a new CMOS storage cell based on latch redundancy has been analyzed using a laser beam simulation. We detected and investigated topology-dependent upset mechanisms due to charge collection at two sensitive nodes using a laser excitation between the nodes. Compact upset-immune device topologies are proposed, using spacing and isolation techniques for simultaneously sensitive node pairs, to achieve high immunity levels required in critical applications