SEE sensitivity trends in non-hardened high density SRAMs with sub-micron feature sizes

Abstract

We report on single event upset (SEU) and single event latchup (SEL) sensitivities under irradiation by protons and heavy ions for a variety of non-hardened high density static random access memories (SRAMs) with sub-micron feature sizes. The results are compared with previously measured sensitivities for similar devices with larger features. We discuss the sensitivity trends with temperature and examine other effects such as stuck bits.0-7803-8127-0/03/$17.00 (C) 2003 IEEE

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

“…First of all, the sensitivity depends on the power supply values: the lower the power supply value, the higher the probability of an SEU [27], [32], [33]. Besides, other works have found a little dependence on the temperature [34]. The clock frequency also influences the SER value although some experimental results disagree.…”

Evaluating Constraints on Heavy-Ion SEE Susceptibility Imposed by Proton SEE Testing and Other Mixed Environments

“…One way of avoiding these limitations is to use independent data to bound the limiting SEL cross section or to show that if the device is susceptible, σ vs. LET/LET EQ most likely rises rapidly near threshold (small w and s). Although a review of recent literature [11,12] finds that most SEL limiting cross sections are less than 10 −4 cm 2 (equating to < 2-3E-5 SELs per day in the ISS environment), some analog to digital converters had limiting cross sections on the order of 10 −3 cm 2 , [11] and some SRAMs [12] had cross sections >10 −2 cm 2 . Moreover, reference [13] found that even for similar devices in a single fabrication process from a single vendor, SEL cross sections did not follow a well behaved, compact distribution.…”

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

“…In this regard, note also that a large-scale study on simulating single-event displacement damage has been conducted in recent years [55]- [57]. [19] 280 250 210 200 180 Bulk-Planar SEU [20] 500 350 250 180 130 90 Bulk-Planar SEU [21] 350 280 180 Bulk-Planar SEU [22] 600 350 250 180 130 Bulk-Planer, Bulk-Fin SEU, SET [11] 500 120 90 SiGe BiCMOS SET [39] 14 10 Bulk-Fin SEU [40] 16 7 Bulk-Fin SEU * Includes DRAMs. ‡ Silicon-On-Sapphire (SOS) structures were also examined.…”