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With the semiconductor manufacturing development following the trend into very-deep sub-micron technologies and thus making Moore's law a reality, the decrease in node size introduces new defect mechanisms in manufacturing. Still, the strict quality requirements especially related to the automotive industry stay the same. Traditional fault models like stuck-at and transition delay models which have been used for the digital logic of System-on-Chip designs may be successful in detecting most of the manufacturing defects, but not all of them. In this paper, the new Cell Aware fault model, which has been introduced by Mentor Graphics®, is being evaluated for usage in the automotive design process of Freescale™. Using a state-of-the-art microcontroller product manufactured in a CMOS 55nm process technology, the fault model is evaluated for test coverage and test cost (pattern count) and compared against the traditional fault models used by Freescale. The analysis is carried out by performing several experiments, especially focusing on reducing the test pattern count overhead.

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