Improved Handling of False and Multicycle Paths in ATPG

Vorisek, V.; Swanson, Bruce; Tsai, Kun-Han; Goswami, Dhiraj

doi:10.1109/vts.2006.38

Cited by 15 publications

(8 citation statements)

References 11 publications

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“…At-speed scan patterns typically consist of a relatively slow scan operation followed by two or more fast clock pulses applied at or near functional frequency [7][8] [9] [10]. One of the challenges in generating atspeed scan tests is to avoid false failures on the tester due to exercising paths that are not designed to propagate logic values within a single clock cycle [1] [2][3] [6] [11]. These paths are known as timing exception paths, and they include false paths, multicycle paths, and conditional false paths.…”

Section: Introductionmentioning

confidence: 99%

“…Second, it must consider the stable transitions of multicycle paths with different cycle count and capture the transitions right after they are stable to detect at-speed faults. This is the first paper the authors aware of describing the at-speed test for the multicycle paths A path-oriented approach to handle timing exception paths during at-speed scan pattern generation has been proposed in [2] to handle the setup timing exception paths. In [3], the case studies on various types of timing exception paths in SDC are illustrated.…”

Section: Introductionmentioning

confidence: 99%

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Multicycle-aware At-speed Test Methodology

Tsai

Lin

2013

2013 22nd Asian Test Symposium

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Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multicycle-aware At-speed Test Methodology

Tsai

Lin

2013

2013 22nd Asian Test Symposium

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“…A method to handle false and multicycle paths during atspeed automatic test pattern generation (ATPG) more accurately was originally proposed in [1]. In [1], timing exception paths with only setup violations were considered.…”

Section: Introductionmentioning

confidence: 99%

“…In [1], timing exception paths with only setup violations were considered. The effect of glitches during per-pattern analysis was not completely addressed.…”

Section: Introductionmentioning

confidence: 99%

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Test generation in the presence of timing exceptions and constraints

Goswami

Tsai

Kassab

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.

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Improved test methodology for multi-clock domain SoC ATPG testing

Ooi

Ang

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Improved Handling of False and Multicycle Paths in ATPG

Cited by 15 publications

References 11 publications

Multicycle-aware At-speed Test Methodology

Multicycle-aware At-speed Test Methodology

Test generation in the presence of timing exceptions and constraints

Improved test methodology for multi-clock domain SoC ATPG testing

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