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The focus of Software Development Effort Estimation (SDEE) is to precisely predict the estimation of effort and time required for successfully developing a software project. From the past few years, data-intensive applications with a huge back-end part are contributing to the overall effort of projects. Therefore, it is becoming more important to add the back-end part to the SDEE process. This paper proposes an Evolutionary Learning (EL) based hybrid artificial neuron termed as dilationerosion perceptron (DEP) framework from the mathematical morphology (MM) having its foundation in complete lattice theory (CLT) for solving the SDEE problem. In this work, we used the DEP (CMGA) model utilizing a chaotically modified genetic algorithm (CMGA) for the construction of DEP parameters. The proposed method uses the ER diagram artifacts such as aggregation, specialization, generalization, semantic integrity constraints, etc. for calculating the SDEE of back-end part of the business software. Furthermore, the proposed method was tested over two different datasets, one is existing and the other one is a self-developed dataset. The performance of the given method is then evaluated by three popular performance metrics, exhibiting better performance of the DEP (CMGA) model for solving the SDEE problems.

Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test generation has been presented in [1]. This paper presents a unified and complete algorithm for computing test responses in the presence of timing exceptions with both setup and hold violations, and Boolean timing constraints. The new algorithm analyzes all possible effects of glitches in the circuit. It resolves pessimism in the case of multiple interacting timing exception paths. The new method significantly reduces the number of unknowns in the test responses, resulting in improved test coverage and test compression. The new method can be applied to 1) any fault model, 2) any test pattern, 3) any simulation environment, and/or 4) any test generator.