Test generation in the presence of timing exceptions and constraints

Goswami, Dhiraj; Tsai, Kun-Han; Kassab, Mark; Rajski, J.

doi:10.1145/1278480.1278653

Cited by 8 publications

(1 citation statement)

References 12 publications

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“…This SDC file contains the timing constraint information related to the design and should be the same as the constraint file used for synthesis. SDC file includes the clock definitions for design, input/output delay, max/min delay, and timing exceptions [7] such as multicycle path, false path, set-caseanalysis, and set disabling time. The SDC file defines all timing constraints included for both setup and hold.…”

Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

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Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Multicycle-aware At-speed Test Methodology

Tsai

Lin

2013

2013 22nd Asian Test Symposium

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Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

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Race and Glitch Handling: A Test Perspective

Tsai

2019

2019 IEEE International Test Conference in Asia (ITC-Asia)

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Test generation in the presence of timing exceptions and constraints

Cited by 8 publications

References 12 publications

An effective way to generate the shift timing constraints and sanity checks

An effective way to generate the shift timing constraints and sanity checks

Multicycle-aware At-speed Test Methodology

Race and Glitch Handling: A Test Perspective

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