We present a Cartesian I/Q modulator based on dual 10-bit RF-DACs. Non-overlapping LO signals and a segmented RF-DAC architecture with scaled bit currents contribute to good linearity and allow low-complexity DPD. Unit-cell flip-flops with a balanced clock distribution enable a high sample rate. Drive slope control for data switches reduce out-of-band emissions. Implemented in 22 nm FDSOI CMOS, the modulator operates up to 26 GHz with a maximum sample rate of 11 GS/s. The modulator is used to demonstrate transmission of a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and an OFDM signal comprising four aggregated 400-MHz 64QAM channels at an EVM of 6.43 %. The results demonstrate the potential of the proposed modulator architecture for realization of ultra wideband transmitters for high performance mm-wave systems.

We describe a 2×6 bit Cartesian RF IQ-modulator, implemented on 0.15 mm 2 in a 22 nm FDSOI CMOS technology. Measurements show a 3 dB bandwidth of 17-24 GHz and a saturated output power of 10.4 dBm with a peak drain efficiency of 15.6 %. The IQ-modulator has been verified up to 8 GS/s. To the best of our knowledge, this is the highest-frequency CMOS RF IQ-modulator using sub-50 %-duty-cycle LO signals, and the highest sample rate reported for >3 bit fully integrated Cartesian IQ-modulators.

Analog and/or digital predistortion may be used to linearize power amplifiers (PAs) at the cost of additional hardware. We present a novel scheme which uses segmented non-linear RF-DACs to linearize PAs at no additional hardware cost. An expanding segmented scaling chosen at design time may be adjusted using DAC bias, allowing linearization to be adapted. Simulations demonstrate the robustness and flexibility of the approach, achieving excellent overall linearity over a large range of DAC and PA bias conditions.

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