Abstract-The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce the maximum temperature and wire congestion of 3D circuits without compromising total wirelength and via count. Our approach consists of two phases. First, we use a multi-level min-cut placement with a modified gain function for local wire congestion and dynamic power consumption reduction. Second, we perform simulated annealing together with full-length thermal analysis and global routing for global wire congestion and maximum temperature reduction. Our experimental results show smooth tradeoff among congestion, temperature, wirelength, and via.

Delay and power minimization are two important objectives in the current circuit designs. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a framework for multi-level global placement with retiming, targeting simultaneous delay and power optimization. We propose GEO-P for power optimization and GEO-PD algorithm for simultaneous delay and power optimization and provide smooth wirelength, power and delay tradeoff. In GEO-PD, we use retiming based timing analysis and visible power analysis to identify timing and power critical nets and assign proper weights to them to guide the multi-level optimization process. We show an effective way to translate the timing and power analysis results from the original netlist to a coarsened subnetlist for effective multi-level delay and power optimization. Our GEO-P achieves 27% average power improvement and our GEO-PD provides gains in both delay and power improvement. To the best of our knowledge, this is the first paper addressing simultaneous delay and power optimization in multi-level global placement.