This study presents a reconfigurable quasi-cyclic low density parity check (QC-LDPC) decoder for IEEE 802.16e worldwide interoperability for microwave access and IEEE 802.11n wireless fidelity communication standards. It supports multiple code-rates of 1/2, 2/3, 3/4, 5/6 and its architecture has been designed based on column layered decoding technique to enhance the convergence speed. The authors have suggested a register file based approach to handle the shift property of the modified parity check matrix and a modified version of the matrix permutation method has been introduced to reduce the number of check nodes which handle multiple messages. In addition, parallel processing has been incorporated in the decoder architecture to attain higher achievable throughput. This QC-LDPC decoder is implemented in 90 nm CMOS process and is post-layout simulated. It can achieve a throughput of 796 Mbps for a code-rate of 5/6. With 0.9 V supply, it consumes 146 mW of total power at 149 MHz clock frequency. 2 Theoretical background Consider a PCM, which is denoted by H, with R rows and C columns representing binary QC-LDPC code. Columns and rows of PCM represent VNUs and CNUs respectively. A non-zero entry (i.e. '1') IET Circuits, Devices & Systems

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This paper presents a baseband architecture consisting of a complex IQ bandpass filter followed by a 3-stage Variable Gain Amplifier (VGA) designed for multi-standard navigation receivers. A new dc offset correction circuit based on a low-pass feedback network is proposed for high gain VGA to cancel its own dc offset and that of the previous stage. The presented baseband circuits are incorporated into a multi-standard navigation receiver fabricated in 65 nm CMOS technology. The filter and VGA together provide a programmable gain of 43 dB over a tunable bandwidth of 2-4 MHz with less than 1-dB in-band attenuation. Occupying 0.39 mm 2 on-chip area, the filter and VGA draw a maximum current of 7 mA from a 1.2-V supply