The design of a full Broadcast + Interactive Services compliant 2 nd Generation Satellite Digital Video Broadcast (DVB-S2) [1] codec is presented. Previously published silicon implementations respecting this stringent standard reports power consumption between 800mW and 1020mW [5]. This large power consumption is related to long Low-Density Parity Check (LDPC) codes [2] and has always been a barrier to the adoption of long LDPC codes in wireless transmissions for portable devices. This silicon demonstrates a drastic reduction of power consumption when decoding HDTV frames and shows that long LDPC codes can also be used on portable devices to allow close-to-Shannon-limit transmissions.This chip includes a Forward Error Correction (FEC) block and a packet delineator, plus some extra blocks for functional auto-test. The FEC is composed of a BCH [3] codec, an LDPC codec, and a channel (de)interleaver. This FEC supports all eleven DVB-S2 code rates ( different block sizes (64800 and 16200 bits), and all 4 digital modulation constellations (QPSK, 8PSK, 16APSK, 32APSK). The LDPC architecture is shown in Fig. 16.3.1. It consists of a dedicated vector processor with a parallelism level of 180. It has been designed using Matlab-to-RTL [4] flow. Rigorous algorithmic and architectural exploration allowed a reduction in the level of parallelism by a factor 2 versus a previously published DVB-S2 FEC [5], as well as a DVB-S2 decoder [7]. It also allowed the clock frequency to be reduced by nearly a factor of 2 versus previous implementations (174MHz instead of 300MHz to produce a 135Mb/s bit stream). The BER has been improved versus the best known published DVB-S2 FEC [6] due to special decoding graph insights and usage of the belief propagation algorithm ( Fig. 16.3.2).The need to minimize power has been the driver influencing algorithmic choices: iteration management including early termination, parallelism level, RAM partitioning, etc. A dedicated power management block has been added to limit the power consumption to a minimum depending on transmission noise level. Moreover, 51% of registers use a gated clock by automated insertion at the synthesis level and dedicated insertion for memory BIST at the RTL level. Figure 16.3.3 shows power consumption values for each code rate of the standard (64800b frames) depending on the noise level (C/N). The vertical lines highlight the power consumption values in worst-case noisy transmission, still ensuring error-free transmission. Note that power consumption decreases when noise decreases (i.e., C/N increases). The power consumption ranges between 130mW and 476mW depending on the code rate when running at 135Mb/s (i.e., 174MHz clock). This is a 6.5× improvement versus paper [5]. Under noisy conditions, power consumption decreases by a factor 2.1×. It is important to note that HDTV transmission only requires 105Mb/s (i.e., 135MHz clock) with power figures between 100mW and 150mW in medium and low noise transmissions, showing for the first time to our knowledge, an acceptable power con...

Abstract. This paper deals with an electrical modelling and optimization of a thermal energy harvester dedicated to power autonomous systems. Such devices based on bimetal strips and piezoceramics turn thermal gradients into electricity by a two-step conversion mechanism. This work focuses first on a demonstration of a ST-WSN (GreenNet demonstration platform) supplied by the harvester to validate, for the first time, the harvesters viability. That demonstration focuses attention on the need for an optimized power management circuit for piezoelectric generators able to reach output voltages up to 20V. The work deals then with the proposal of an equivalent lumped element model of the piezoelectric transducer with its SPICE implementation to enable the optimization of a dedicated power management circuit based on the Pulsed Synchronous Charge Extractor (PSCE). Simulations using the SPICE model and the power management circuit lead to an increased extracted power by 144%. IntroductionThe field of energy harvesting has become a predominant research area, especially, with the development of wireless sensors and communication node networks. Industrial and health monitoring, smart buildings, internet of things, these are some domains where node networks can be widely used. However, the impractical aspect of wired systems and the problems related to the power supply by short-lifetime batteries are raised for those applications. This brought attention on ambient energy harvesters and explains the great interest in energy scavenging devices over the last years. In this paper, a thermal energy harvester previously presented in [1,2,3] is studied. The harvester is based on coupling a bimetal to a piezoelectric transducer where a two-step conversion mechanism occurs. The heat flowing through the bimetal strip is converted into mechanical oscillations insuring the thermo-mechanical conversion; the second step consists in the conversion of the bimetallic strip impacts into electricity by a piezoelectric transducer. A bimetal strip is characterized by two equilibrium positions as shown in Fig. 1(a). Due to the bimetal thermo-mechanical bi-stability explained in [4], the bimetal snaps up and hits the piezoelectric membrane once its temperature raises and reaches a threshold temperature called the snap-up temperature. At that point, the bimetal is at its upper-position and releases a part of its energy to the piezoelectric. While being in contact with the piezoelectric acting as a cold surface, the temperature of the bimetal decreases until it reaches a certain snapping-back temperature that makes it switch-back to its initial

International audienceThe quality of transmission in digital communication systems is usually measured by Frame Error Rate (FER). The time taken by standard Monte Carlo (MC) simulation to estimate the FER increases exponentially with the increase in Signal-to-Noise Ratio (SNR). In this correspondence, we present an Adaptive Importance Sampling (AIS) technique inspired by statistical physics called Fast Flat Histogram (FFH) method to evaluate the performance of LDPC codes with a reduced simulation time. The FFH method employs Wang Landau algorithm based on a Markov Chain Monte Carlo (MCMC) sampler and we managed to decrease the simulation time by a factor of 13 to 173 for LDPC codes with block lengths up to 2640 bits

Standard Monte Carlo (SMC) simulation is employed to evaluate the performance of Forward Error Correcting (FEC) codes.This performance is in terms of the probability of error during the transmission of information through digital communication systems. The time taken by SMC simulation to estimate the FER increases exponentially with the increase in Signal-to-Noise Ratio (SNR). We hereby present an improved version of Fast Flat Histogram (FFH) method, an Adaptive Importance Sampling (AIS) technique inspired by algorithms existing in statistical physics. We show that the improved FFH method employing Wang Landau algorithm based on a Markov Chain Monte Carlo (MCMC) sampler reduces the simulation time of the performance evaluation of complex FEC codes having different code rates.

ISBN 978-1-4244-5773-1International audienceFollowing the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at 0.330V, 600kHz frequency and needs 1.27nJ to decode a 252bits frame. With 14% of extra power compared to typical process, applying forward bias enables to compensate temperature and skewed process effects, regaining 150mV minimum operating voltage