A 360mW 105Mb/s DVB-S2 Compliant Codec based on 64800b LDPC and BCH Codes enabling Satellite-Transmission Portable Devices

Abstract

The design of a full Broadcast + Interactive Services compliant 2 nd Generation Satellite Digital Video Broadcast (DVB-S2) [1] codec is presented. Previously published silicon implementations respecting this stringent standard reports power consumption between 800mW and 1020mW [5]. This large power consumption is related to long Low-Density Parity Check (LDPC) codes [2] and has always been a barrier to the adoption of long LDPC codes in wireless transmissions for portable devices. This silicon demonstrates a drastic reduction of power consumption when decoding HDTV frames and shows that long LDPC codes can also be used on portable devices to allow close-to-Shannon-limit transmissions.This chip includes a Forward Error Correction (FEC) block and a packet delineator, plus some extra blocks for functional auto-test. The FEC is composed of a BCH [3] codec, an LDPC codec, and a channel (de)interleaver. This FEC supports all eleven DVB-S2 code rates ( different block sizes (64800 and 16200 bits), and all 4 digital modulation constellations (QPSK, 8PSK, 16APSK, 32APSK). The LDPC architecture is shown in Fig. 16.3.1. It consists of a dedicated vector processor with a parallelism level of 180. It has been designed using Matlab-to-RTL [4] flow. Rigorous algorithmic and architectural exploration allowed a reduction in the level of parallelism by a factor 2 versus a previously published DVB-S2 FEC [5], as well as a DVB-S2 decoder [7]. It also allowed the clock frequency to be reduced by nearly a factor of 2 versus previous implementations (174MHz instead of 300MHz to produce a 135Mb/s bit stream). The BER has been improved versus the best known published DVB-S2 FEC [6] due to special decoding graph insights and usage of the belief propagation algorithm ( Fig. 16.3.2).The need to minimize power has been the driver influencing algorithmic choices: iteration management including early termination, parallelism level, RAM partitioning, etc. A dedicated power management block has been added to limit the power consumption to a minimum depending on transmission noise level. Moreover, 51% of registers use a gated clock by automated insertion at the synthesis level and dedicated insertion for memory BIST at the RTL level. Figure 16.3.3 shows power consumption values for each code rate of the standard (64800b frames) depending on the noise level (C/N). The vertical lines highlight the power consumption values in worst-case noisy transmission, still ensuring error-free transmission. Note that power consumption decreases when noise decreases (i.e., C/N increases). The power consumption ranges between 130mW and 476mW depending on the code rate when running at 135Mb/s (i.e., 174MHz clock). This is a 6.5× improvement versus paper [5]. Under noisy conditions, power consumption decreases by a factor 2.1×. It is important to note that HDTV transmission only requires 105Mb/s (i.e., 135MHz clock) with power figures between 100mW and 150mW in medium and low noise transmissions, showing for the first time to our knowledge, an acceptable power con...

An adaptive low-power LDPC decoder using SNR estimation

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High-speed conflict-free layered LDPC decoder for the DVB-S2, -T2 AND -C2 standards

“…The system decodes long frames of code rates 1/2, 2/3, 3/4, 4/5 and 5/6. The average number of decoding iterations is reduced to 15 thanks The implementation of a layered decoder for the DVB-S2 standard was considered in [8] and [19]. Table 1 compares these implementations in terms of parallelism, air throughput, signal width and total area.…”

Architecture and Finite Precision Optimization for Layered LDPC Decoders

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