The use of adiabatic passage techniques to mediate particle transport through real space, rather than phase space, is becoming an interesting possibility. We have investigated the properties of coherent tunneling adiabatic passage (CTAP) with alternating tunneling matrix elements. This coupling scheme, not previously considered in the donor in silicon paradigm, provides an interesting route to long-range quantum transport. We introduce simplified coupling protocols and transient eigenspectra as well as a realistic gate design for this transport protocol. Using a pairwise treatment of the tunnel couplings for a five-donor device with 30 nm donor spacings, 120 nm total chain length, we estimate the timescale required for adiabatic operation to be approximately 70 ns, a time well within the measured electron spin and estimated charge relaxation times for phosphorus donors in silicon.

The single electron transistor (SET) offers unparalled opportunities as a nano-scale electrometer, capable of measuring sub-electron charge variations. SETs have been proposed for read-out schema in solid-state quantum computing where quantum information processing outcomes depend on the location of a single electron on nearby quantum dots. In this paper we investigate various geometries of a SET in order to maximize the device's sensitivity to charge transfer between quantum dots. Through the use of finite element modeling we model the materials and geometries of an Al/Al 2 O 3 SET measuring the state of quantum dots in the Si substrate beneath. The investigation is motivated by the quest to build a scalable quantum computer, though the methodology used is primarily that of circuit theory. As such we provide useful techniques for any electronic device operating at the classical/quantum interface.

Single Electron Transistors (SETs) are nanoscale electrometers of unprecedented sensitivity, and as such have been proposed as read-out devices in a number of quantum computer architectures. We show that the functionality of a standard SET can be multiplexed so as to operate as both read-out device and control gate for a solid-state qubit. Multiplexing in this way may be critical in lowering overall gate densities in scalable quantum computer architectures.

The Kane (Kane B E 1998 Nature 393 133) solid-state quantum computer aims to exploit as qubits an array of31P nuclear spins embedded in a silicon matrix. A proposed scheme for readout of a qubit spin state relies on measurement of the associated spin state of its donor electron, by attempting to induce and detect, using a single-electron transistor (SET), spin-polarized motion of the electron to an adjacent donor site. The sensitivity required of a SET for detection of sub-surface electronic charge motion in a MOS architecture is examined by simulation of the capacitive coupling of the buried charge to the SET device. It is shown that the SET can support readout of the qubit electronic charge states within the appropriate electron spin relaxation time. This paper presents a novel application of Technology Computer Aided Design, which presents itself as a valuable tool for the design of nanoscale device architectures employing precision electrometry for readout of quantum logic states.