Designing and Modeling for Power Integrity / Swaminathan M.; Chung D.; Grivet-Talocia S.; Bharath K.; Laddha V.; Xie J.Abstract-After providing an overview of the state-of-the-art in power distribution design and modeling, this paper focuses on return path discontinuities (RPDs) for I/O signaling. After briefly describing their importance in the context of simultaneous switching noise, a specific case of RPD based on via discontinuities is discussed in detail in the context of both the frequency-and timedomain waveforms using a test vehicle. The modeling of RPD in practical packages and printed circuit boards is addressed along with substrate coupling due to nonideal reference planes. Finally, a high-impedance power distribution scheme for I/O signaling is presented that can potentially solve a number of RPD-related problems, followed by future challenges.Index Terms-Macro-modeling, passivity, power distribution, power integrity, return path discontinuity, signal integrity.

Timing margin (jitter) and voltage margin (noise) are the main bottlenecks in the performance of high speed digital channels. The simultaneous switching noise (SSN) induced by the return path discontinuities such as signal via transitions and plane cutouts is a major source of jitter and noise introduced by the package and the printed circuit boards on the signal interconnects of these channels. In this paper, we present a new methodology to correlate SSN induced signal jitter and noise with the power distribution network (PDN) impedance by studying the exact mechanism of how the PDN impedance affects signal jitter and voltage margin. Further, we validate the analysis by both simulations and measurements and suggest design practices to reduce jitter and noise on the signal.