The 21st century is the era of Ubiquitous Computing where computing devices are present everywhere in our lives. To satisfy the development of this tendency, many hardware platforms have been proposed for developing Ubiquitous devices. Among them, T-Engine, an open standardized development platform for embedded systems, is one of the most popular platforrms. It is nowadays compatible with embedded equipments for a wide range of fields. In Vietnam, T-Engine has just been introduced for 4 years. However, most of the ubiquitous applications using T-Engine are developed restrictively based on the standard hardware of T-Engine. One issue that arises is the necessity of a solution to expand T-Engine hardware and use it to control automatic systems to satisfy different types of Ubiquitous devices. This research is to propose an approach to use T-Engine in the Ubiquitous Devices that require the attachment of the additional hardware as well as the complicated control mechanism with real time constraints. In this research, we proposed an expanding solution T-Engine through the extension bus. Besides that, we consider the timing problems in bus transaction and problems in real-time programming. A simple robot demonstration has also been designed and implemented to prove the feasibility of our model. This approach will open up a new tendency of developing complicated Ubiquitous devices using T-Engine in Vietnam.

Contrary to the synchronous circuits, the asynchronous circuits operate with a mechanism of local synchronization (without clock signal). For many years, they showed their relevance with respect to the synchronous circuits thanks to their properties of robustness, low power, low noise and modularity. However, the lack of design methods and associated tools prevents them from being widely spread. This paper deals with a new design methodology for integrated asynchronous circuits and EDA tools. The suggested design method allows on one hand to model circuits in a highlevel language, and on the other hand to generate circuits using only elementary logical gates and Muller gates. This method was prototyped by the development of an EDA design tool for asynchronous circuits. The combination of design methodologies and supporting tools creates a design framework for asynchronous circuits, namely PAiD ("Project of Asynchronous Circuit Design"). This framework allows compilation and synthesis of circuits, described by high-level language ADL ("Asynchronous Description Language"), to generate asynchronous circuits. The result of the synthesizer is a functional netlist of the circuits. This netlist can be then mapped to a specific-technology gate library for asynchronous circuits. During the design process, the circuit can be tested through the simulation process in different levels of abstraction.

Handwriting character recognition is an important research topic which has various applications in surveillance, radar, robot technology... In this paper, we propose the implementation of the handwriting character recognition using off-line handwriting recognition. The approach consists of two steps: to make thin handwriting by keeping the skeleton of character and reject redundant points caused by humam’s stroke width and to modify direction method which provide high accuracy and simply structure analysis method to extract character’s features from its skeleton. In addition, we build neural network in order to help machine learn character specific features and create knowledge databases to help them have ability to classify character with other characters. The recognition accuracy of above 84% is reported on characters from real samples. Using this off-line system and other parts in handwriting text recognition, we can replace or cooperate with online recognition techniques which are ususally applied on mobile devices and extend our handwriting recognition technique on any surfaces such as papers, boards, and vehicle lisences as well as provide the reading ability for humanoid robot.

FPGA device is a dominant implementation medium for digital circuits. Unfortunately, they do not support asynchronous circuits because of the lack of asynchronous circuit elements such as Muller gates, etc. In this paper, new efficient approaches are proposed to prototype asynchronous circuits on Look-Up Table-based (LUT) FPGA rapidly. The developed techniques are based on building of elements which play an important role in asynchronous circuits. The hazard-free elements are predefined in libraries in HDL and EDIF format. Timing and/or area constraints for place&route tool are automatically generated to map the asynchronous elements on suitable FPGA’s logic blocks. Several FPGA devices such as Altera, Xilinx and Actel could be used as target for the implementation.